? semiconductor components industries, llc, 2004 april, 2004 ? rev. 7 1 publication order number: mtd2955v/d mtd2955v power mosfet 12 a, 60 v p?channel dpak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. features ? avalanche energy specified ? i dss and v ds(on) specified at elevated temperature ? pb?free packages are available maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss 60 vdc drain?to?gate voltage (r gs = 1.0 m ) v dgr 60 vdc gate?to?source voltage ? continuous ? non?repetitive (t p 10 ms) v gs v gsm 20 25 vdc vpk drain current ? continuous drain current ? continuous @ 100 c drain current ? single pulse (t p 10 s) i d i d i dm 12 8.0 42 adc apk total power dissipation derate above 25 c total power dissipation @ 25 c (note 2) p d 60 0.4 2.1 watts w/ c watts operating and storage temperature range t j , t stg ?55 to 175 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, peak i l = 12 apk, l = 3.0 mh, r g = 25 ) e as 216 mj thermal resistance ? junction to case ? junction to ambient (note 1) ? junction to ambient (note 2) r jc r ja r ja 2.5 100 71.4 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. when surface mounted to an fr4 board using the minimum recommended pad size. 2. when surface mounted to an fr4 board using the 0.5 sq.in. pad size. d s g 12 a, 60 v r ds(on) = 185 m (typ) p?channel http://onsemi.com dpak?3 case 369c style 2 1 2 3 4 dpak?3 case 369d style 2 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information see general marking information in the device marking section on page 7 of this data sheet. device marking information
mtd2955v http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (cpk 2.0) (note 5) (v gs = 0 vdc, i d = 0.25 madc) temperature coefficient (positive) v (br)dss 60 ? ? 58 ? ? vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? ? ? 10 100 adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (cpk 2.0) (note 5) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 2.0 ? 2.8 5.0 4.0 ? vdc mv/ c static drain?to?source on?resistance (cpk 1.5) (note 5) (v gs = 10 vdc, i d = 6.0 adc) r ds(on) ? 0.185 0.230 drain?to?source on?voltage (v gs = 10 vdc, i d = 12 adc) (v gs = 10 vdc, i d = 6.0 adc, t j = 150 c) v ds(on) ? ? ? ? 2.9 2.5 vdc forward transconductance (v ds = 10 vdc, i d = 6.0 adc) g fs 3.0 5.0 ? mhos dynamic characteristics input capacitance c iss ? 550 770 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 200 280 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 50 100 switching characteristics (note 4) turn?on delay time t d(on) ? 15 30 ns rise time (v dd = 30 vdc, i d = 12 adc, v gs =10vdc t r ? 50 100 turn?off delay time v gs = 10 vdc, r g = 9.1 ) t d(off) ? 24 50 fall time g ) t f ? 39 80 gate charge q t ? 19 30 nc (v d s = 48 vdc, i d = 12 adc, q 1 ? 4.0 ? (v ds = 48 vdc , i d = 12 adc , v gs = 10 vdc) q 2 ? 9.0 ? q 3 ? 7.0 ? source?drain diode characteristics forward on?voltage (note 3) (i s = 12 adc, v gs = 0 vdc) (i s = 12 adc, v gs = 0 vdc, t j = 150 c) v sd ? ? 1.8 1.5 3.0 ? vdc reverse recovery time t rr ? 115 ? ns (i =12adc v = 0 vdc t a ? 90 ? (i s = 12 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t b ? 25 ? reverse recovery stored charge di s /dt 100 a/ s) q rr ? 0.53 ? c internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d ? ? 3.5 4.5 ? ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 7.5 ? nh 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperature. 5. reflects typical values. c pk = max limit ? typ 3 x sigma
mtd2955v http://onsemi.com 3 typical electrical characteristics figure 1. on?region characteristics figure 2. transfer characteristics figure 3. on?resistance versus drain current and temperature figure 4. on?resistance versus drain current and gate voltage figure 5. on?resistance variation with temperature figure 6. drain?to?source leakage current versus voltage 012345 0 15 25 v ds , drain-to-source voltage (volts) i d , drain current (amps) 24 6 810 0 9 18 24 i d , drain current (amps) v gs , gate-to-source voltage (volts) t j = 25 c v ds 10 v t j = -55 c 25 c 100 c v gs = 10 v 9 v 8 v 6 v 5 v 7 v 5 10 20 3579 3 12 21 678910 15 6 r ds(on) , drain-to-source resistance (ohms) 03 6 15 24 0 0.10 0.20 0.30 r ds(on) , drain-to-source resistance (ohms) 0 6 21 24 0.050 0.075 0.200 0.250 i d , drain current (amps) i d , drain current (amps) t j = 25 c v gs = 10 v t j = 100 c 25 c -55 c 12 21 3 12 15 0.05 0.15 0.25 0.100 0.225 0.125 v gs = 10 v 15 v 18 9 0.35 0.40 0.175 918 0.150 r ds(on) , drain-to-source resistance (normalized) -50 0.6 0.8 1.2 1.6 020 5060 10 100 1000 t j , junction temperature ( c) v ds , drain-to-source voltage (volts) i dss , leakage (na) -25 0 25 50 75 100 125 150 v gs = 0 v v gs = 10 v i d = 6 a 10 30 40 1.0 1.4 t j = 125 c 175 0.4 0.2 0 1.8 2.0 100 c
mtd2955v http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. figure 7. capacitance variation 10 0 10 15 25 gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 1200 1000 800 600 400 200 0 20 c iss c oss c rss 55 c iss c rss 1600 1800 1400
mtd2955v http://onsemi.com 5 drain?to?source diode characteristics figure 8. gate?to?source and drain?to?source voltage versus total charge figure 9. resistive switching time variation versus gate resistance figure 10. diode forward voltage versus current v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) r g , gate resistance (ohms) 1 10 100 t, time (ns) v dd = 30 v i d = 12 a v gs = 10 v t j = 25 c t f t d(off) 0 q t , total charge (nc) 2468 20 i d = 12 a t j = 25 c v gs 1000 100 10 1 10 6 2 0 1 8 4 30 27 24 21 18 15 0 v ds 18 14 qt q1 q2 q3 16 10 12 t d(on) t r 7 3 9 5 12 3 6 9 0.5 0.7 1.1 1.9 v sd , source-to-drain voltage (volts) i s , source current (amps) v gs = 0 v t j = 25 c 0 6 8 10 12 4 0.9 1.3 1.5 2 1.7 5 7 9 11 3 1 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance?general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
mtd2955v http://onsemi.com 6 safe operating area figure 11. maximum rated forward biased safe operating area figure 12. maximum avalanche energy versus starting junction temperature figure 13. thermal response figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b t j , starting junction temperature ( c) e as , single pulse drain-to-source 0.1 10 100 v ds , drain-to-source voltage (volts) avalanche energy (mj) i d , drain current (amps) 25 50 75 100 125 v gs = 15 v single pulse t c = 25 c i d = 12 a 1.0 150 1.0 100 0.1 0 75 25 10 dc 100 s 1 ms 10 ms r ds(on) limit thermal limit package limit 50 175 100 125 150 175 200 225 t, time (s) r(t), normalized effective transient thermal resistance r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0 0.1 0.01 0.2 d = 0.5 0.05 0.01 single pulse 0.1 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.02
mtd2955v http://onsemi.com 7 ordering information device package shipping 2 mtd2955v dpak?3 75 units/rail mtd2955vg dpak?3 (pb?free) 75 units/rail mtd2955v?1 dpak?3 75 units/rail mtd2955v?1g dpak?3 (pb?free) 75 units/rail mtd2955vt4 dpak?3 2500 tape & reel mtd2955vt4g dpak?3 (pb?free) 2500 tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. dpak?3 case 369c style 2 marking diagrams 1 gate 3 source 2 drain 4 drain 2955v device code y = year ww = work week yww t 2955v yww t 2955v 1 gate 3 source 2 drain 4 drain dpak?3 case 369d style 2
mtd2955v http://onsemi.com 8 package dimensions dpak?3 case 369c?01 issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch.
mtd2955v http://onsemi.com 9 dpak?3 case 369d?01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ???
mtd2955v http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mtd2955v/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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